Basic VLSI Index – Karanams Academy

Courses

BASIC VLSI - Course Index

BASIC VLSI COURSE

VLSI BASICS

PHYSICAL DESIGN BASICS

RTL DESIGN BASICS

BASIC VLSI

ASIC DESIGN FLOW

DIGITAL ELECTRONICS

VERILOG HDL

PHYSICAL DESIGN BASICS

INTRODUCTION

RTL DESIGN BASICS

INTRODUCTION

DIGITAL ELECTRONICS

1. BASIC CONCEPTS

2. NUMBER SYSTEMS

2.1. Binary

2.2. Octal and conversion

2.3. Hexadecimal and conversion

2.4. BCD

2.5. Gray

2.6. Decimal and conversion

2.7. Binary Addition

2.8. Binary Subtraction

3. LOGIC GATES

3.1. Introduction

3.2. AND

3.3. OR

3.4. NOT

3.5. NAND

3.6. NOR

3.7. XOR

3.8. XNOR

4. REALIZATION OF LOGIC GATES

4.1. AOI to NOR

4.2. AOI to NAND

5. BOOLEAN ALGEBRA

5.1. Boolean Algebra and Operators

5.2. Tautology, Fallacy and Principle of duality

5.3. Boolean Laws

6. K-MAPS

6.1. Max terms, Min terms

6.2. SOP, POS

6.3. 2 variables

6.4. 3 variables

6.5. 4 variables

6.6. 5 variables

7. HALF ADDER

7.1. Using AOI

7.2. Using XOR

8. FULL ADDER

9. HALF SUBTRACTOR

10. MULTIPLEXER

11. DEMULTIPLEXER

12. ENCODER

13. DECODER

14. OTHER COMBINATIONAL CIRCUITS

15. ALU

16. LATCHES

17. GATED LATCH

18. SEQUENTIAL CIRCUIT

19. FLIPFLOPS

20. SR FLIPFLOP

21. D FLIPFLOP

20. SR FLIPFLOP

22. JK FLIPFLOP

23. T FLIPFLOP

24. CONVERSIONS OF FF

25. BINARY UP COUNTER

26. BINARY DOWN COUNTER

27. BINARY UP-DOWN COUNTER

28. BCD OR DECADE COUNTER

29. MOD COUNTER

30. RING COUNTER

31. JOHNSON COUNTER

32. SHIFT REGISTER

33. SERIAL IN SERIAL OUT REGISTER (SISO)

34. SERIAL IN PARALLEL OUT REGISTER (SIPO)

35. PARALLEL IN SERIAL OUT REGISTER (PISO)

36. PARALLEL IN PARALLEL OUT REGISTER (PIPO)

37. UNIVERSAL SHIFT REGISTER

38. FINITE STATE MACHINE (FSM)

39. FIRST IN FIRST OUT REGISTER (FIFO)

40. LAST IN FORST OUT (LIFO)

VERILOG HDL

41. VERILOG HDL INTRO

42. STRUCTURE OF FUNCTIONAL MODULE

43. TYPES OF MODULE STRUCTURES

44. LOGICAL VALUES AND STRENGTHS

45. CONTINOUS ASSIGNMENT

46. OPERATORS

47. GATE PRIMITIVES

48. BEHAVIORAL MODEL

49. PROCEDURAL BLOCK

50. SEQUENTIAL BLOCK

51. PARALLEL BLOCK

52. LOOPING STATEMENT (IF)

53. STRUCTURE OF TESTBENCH MODEL

54. DISPLAY STATEMENTS

55. LEXICAL TOKENS

57. LITERALS

58. SCALAR AND VECTOR

59. PARAMETER

60. ARRAYS

61. FOR LOOP

62. CASE, CASEX, CASEZ LOOP

63. REPEAT LOOP

64. FOREVER LOOP

65. BLOCKING ASSIGNMENT

66. NON-BLOCKING ASSIGNMENT

67. FORCE-RELEASE

68. SYSTEM TASKS

69. COMPILER DIRECTIVES

70. FUNCTIONS AND TASKS

71. SPECIFY BLOCK

72. GENERATE BLOCK

73. UDP

PHYSICAL DESIGN

1. SYNTHESIS

2. PD FLOW

3. FLOORPLAN

4. PLACEMENT

5. CTS (CLOCK TREE SYNTHESIS)

6. ROUTING

7. STA (STATIC TIMING ANALYSIS)

9. SIGNOFF

Communication Address:

Sri Rajarajeshwari Arcade, 3rd Floor,
Veerannapalya, Nagawara,
Bangalore – 560045

Registered Address:

Karanams Academy Pvt. Ltd.
No 125, Nagappa Layout,
Krishnappa Block, Vasanthapura,
Bangalore – 560061

Information

Working Hours

Newsletters

Subscribe to get updates right in your inbox.
We promise to not send you spams.

Copyright © 2020 Karanams Academy All rights reserved.

error: Content is protected !!